tests: add proper checks for clock polarity before and after csn

tests: properly account for soonly rising csn

feat: implement spi model narrow sck check

fix: assumptions about synthesizable code

feat: add csn pulse test and rx, tx disabling test

chore: move spi models to separate file

feat: add tests for clock phase, polarity

feat: tests for multiple transmissions, rx lost

feat: add first basic test

feat: implement initial hdl_spi