tests: add pull up sda, scl behavior

tests: split master i2c functions to separata package

tests: add mcu tests working with slave top designs

chore: add Vivado project for Basys 3 board

chore: fix slave naming in mcu slave designs

feat: add counter and register testing slave top levels

fix: activate pad_io in open drain on enable = 1

feat: add clear_buffer input to tx

tests: add slave testbench

fix: correct delay pulses length

fix: make slave work

feat: add slave top

feat: handle ack in rx, tx

feat(tx): remove unnecessary bit index

chore: add direnv file

tests: add vunit run.py

feat: add stateful sda, scl switch

chore: use process(all) for combinational processes

tests: add tx testbench

fix: tx bugs