~ruther/verilog-riscv-semestral-project

ref: f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes
f8bf441e — Rutherther chore: move default case 1 year, 6 months ago 
                                                                                
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module ram (
  input         clk, we,
  input [31:0]  a, wd,
  output [31:0] rd);

  reg [31:0]    RAM[0:127];

  assign rd = RAM[a[8:2]]; // word aligned

  always @(posedge clk)
    if(we) RAM[a[8:2]] <= wd;

endmodule
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