~ruther/verilog-riscv-semestral-project: src/ram.sv f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3

~ruther/verilog-riscv-semestral-project

ref: f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file