~ruther/verilog-riscv-semestral-project

ref: ee0204c8aee094b0d30256a61ba9400adb01dd5a verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 554 bytes
ee0204c8 — Rutherther feat: pass program to execute by parameter 1 year, 5 months ago
                                                                                
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import cpu_types::*;

module ram (
  input         clk, we,
  input [31:0]  a, wd,
  input [3:0]   write_byte_enable,
  output [31:0] rd);

  reg [31:0]      mask;
  reg [31:0]      memory[128];

  assign rd = memory[a[8:2]]; // word aligned

  always_comb begin
    mask = {
            {8{write_byte_enable[3]}},
            {8{write_byte_enable[2]}},
            {8{write_byte_enable[1]}},
            {8{write_byte_enable[0]}}
            };
  end

  always_ff @ (posedge clk)
    if(we)
      memory[a[8:2]] = (rd & ~mask) | (wd & mask);

endmodule
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