~ruther/verilog-riscv-semestral-project

ref: ee0204c8aee094b0d30256a61ba9400adb01dd5a verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes
ee0204c8 — Rutherther feat: pass program to execute by parameter 2 years ago 
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

waves/
programs/bin/
*.o
*.bin
*.dat