~ruther/verilog-riscv-semestral-project (df876b38b787b7f1e9120775311a0b1a17e2758b): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

df876b38 — Rutherther chore: extend memory 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git