~ruther/verilog-riscv-semestral-project (cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

cc87c7b8 — Rutherther fix(Makefile): make objdump and all testbenches work 1 year, 7 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}