~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 84 bytes
cc87c7b8 — Rutherther fix(Makefile): make objdump and all testbenches work 1 year, 7 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop
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