~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/programs/link.ld -rwxr-xr-x 291 bytes
cc87c7b8 — Rutherther fix(Makefile): make objdump and all testbenches work 1 year, 7 months ago 
                                                                                
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MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

SECTIONS
{
	.text = 0x0;
    .bss : {
        __bss_start = .;
        *(.bss)
        *(COMMON)
        __bss_end = .;
    } > ram
    .stack : {
        __stack_start = .;
        *(.stack)
        __stack_end = .;
    } > ram
}
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