~ruther/verilog-riscv-semestral-project (cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c): programs/add.c

~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 116 bytes

cc87c7b8 — Rutherther fix(Makefile): make objdump and all testbenches work 1 year, 7 months ago

int add(int a, int b)
{
    return a + b;
}

void main()
{
    int a = 20;
    int b = 30;
    int c = add(a, b);
}