~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 verilog-riscv-semestral-project/.envrc -rwxr-xr-x 10 bytes
c5e322db — Rutherther fix: use reg for procedural assignments 1 year, 5 months ago 
                                                                                
1

use flake
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