~ruther/verilog-riscv-semestral-project (c5e322db080e580a25dafe64d29405db34adec57): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

c5e322db — Rutherther fix: use reg for procedural assignments 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git