~ruther/verilog-riscv-semestral-project

ref: bc02aba5f50d84e93657a0601f713d990ecb8f11 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
bc02aba5 — Rutherther fix: make sure alu is zeroed on memory load, write, jump 1 year, 8 months ago 
                                                                                
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.DS_Store
.idea
*.log
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.direnv/
obj_dir/
*.vcd
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