~ruther/verilog-riscv-semestral-project

ref: b7fa590c93b0d8e3e647fb08ecf033e314ece360 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes
b7fa590c — Rutherther chore: add cpu types for various sources 1 year, 7 months ago
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
module ram (
  input         clk, we,
  input [31:0]  a, wd,
  output [31:0] rd);

  reg [31:0]    RAM[0:127];

  assign rd = RAM[a[8:2]]; // word aligned

  always @(posedge clk)
    if(we) RAM[a[8:2]] <= wd;

endmodule
Do not follow this link