~ruther/verilog-riscv-semestral-project: src/ram.sv b7fa590c93b0d8e3e647fb08ecf033e314ece360

~ruther/verilog-riscv-semestral-project

ref: b7fa590c93b0d8e3e647fb08ecf033e314ece360 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file