~ruther/verilog-riscv-semestral-project (a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

a6f4c7fc — Rutherther chore: add new files to compilation list 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}