~ruther/verilog-riscv-semestral-project

ref: 938d89a274f0e1a4c50cc75857cffaa30e2d6f68 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
938d89a2 — Rutherther refactor: change program mem to file prog mem 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd