~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 780 bytes
914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago 
                                                                                
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void main()
{
    int *result_address = 0;
    int *load_address = 0;
    int a = *(load_address);
    int b = *(load_address + 1);

    if (a < b) {
        *(result_address + 0) = 1;
    } else {
        *(result_address + 0) = 2;
    }

    if (a >= b) {
        *(result_address + 1) = 1;
    } else {
        *(result_address + 1) = 2;
    }

    if (a != b) {
        *(result_address + 2) = 1;
    } else {
        *(result_address + 2) = 2;
    }

    if (a == b) {
        *(result_address + 3) = 1;
    } else {
        *(result_address + 3) = 2;
    }

    if (a <= b) {
        *(result_address + 4) = 1;
    } else {
        *(result_address + 4) = 2;
    }

    if (a > b) {
        *(result_address + 5) = 1;
    } else {
        *(result_address + 5) = 2;
    }
}
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