~ruther/verilog-riscv-semestral-project

ref: 773f4b9934627d8574aa6537bf7f289477336fe7 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
773f4b99 — Rutherther test: add simple cpu test 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
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.direnv/
obj_dir/
*.vcd