~ruther/verilog-riscv-semestral-project

ref: 773f4b9934627d8574aa6537bf7f289477336fe7 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
65ab00a4 — Rutherther 2 years ago 
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago 
chore: add gitignore