~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/tests/official d---------
740085c8 — Rutherther fix: lui, force rs1 zero, always add 1 year, 6 months ago
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Makefile
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env/
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official_tests.py
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riscv-tests @ bd0a19c136927eaa3b7296a591a896c141affb6b
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