~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/tests d---------
740085c8 — Rutherther fix: lui, force rs1 zero, always add 1 year, 6 months ago
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comp_list.lst
197 bytes
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custom/
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official/
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run.py
5.0 KiB
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test_types.py
889 bytes
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