~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/tests/official d---------
73cf8a16 — Rutherther tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak 1 year, 6 months ago
..
-rwxr-xr-x
Makefile
618 bytes
d---------
env/
-rwxr-xr-x
official_tests.py
1.4 KiB
m---------
riscv-tests @ bd0a19c136927eaa3b7296a591a896c141affb6b
Do not follow this link