~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/tests d---------
73cf8a16 — Rutherther tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak 1 year, 6 months ago
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comp_list.lst
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custom/
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official/
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run.py
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test_types.py
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