~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
66fd5da9 — Rutherther fix: shift by 5 bits in alu 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd