~ruther/verilog-riscv-semestral-project (65ab00a497a54acf67cb53a211299977d5bc378e): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

65ab00a4 — Rutherther chore: ignore obj_dir, vcd outputs 1 year, 7 months ago

-rwxr-xr-x

.envrc

10 bytes

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.gitignore

52 bytes

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

d---------

src/

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