~ruther/verilog-riscv-semestral-project

ref: 65ab00a497a54acf67cb53a211299977d5bc378e verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
65ab00a4 — Rutherther chore: ignore obj_dir, vcd outputs 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd