~ruther/verilog-riscv-semestral-project

ref: 64d33d2582c219e00b6c1f7573501ee713da0967 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
64d33d25 — Rutherther feat: add program memory 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd