~ruther/verilog-riscv-semestral-project

ref: 64d33d2582c219e00b6c1f7573501ee713da0967 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
65ab00a4 — Rutherther 2 years ago 
chore: ignore obj_dir, vcd outputs
9c81ece2 — Rutherther 2 years ago 
chore: add gitignore