~ruther/verilog-riscv-semestral-project (489df84930a405a04e27485ed89e224ec6fab8b1): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 489df84930a405a04e27485ed89e224ec6fab8b1 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

489df849 — Rutherther chore: import cpu types in stages 1 year, 10 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git