~ruther/verilog-riscv-semestral-project

ref: 38e84297e0e6abf0ec14d91878d5210792b801bd verilog-riscv-semestral-project/tests/custom d---------
38e84297 — Rutherther fix: shift left only by 5 bits 1 year, 6 months ago
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-rwxr-xr-x
custom_tests.py
1.7 KiB
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