~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
2929a779 — Rutherther test: add basic testbenches 3 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd