~ruther/verilog-riscv-semestral-project: .gitignore 2929a779a9d6e451c15f91ac7124f4081e2a04b4

~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes

65ab00a4 — Rutherther 3 years ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 3 years ago

chore: add gitignore