~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/programs/link.ld -rwxr-xr-x 291 bytes
057ee98b — Rutherther chore: add generated bin, obj gitignore files 2 years ago 
                                                                                
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MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

SECTIONS
{
	.text = 0x0;
    .bss : {
        __bss_start = .;
        *(.bss)
        *(COMMON)
        __bss_end = .;
    } > ram
    .stack : {
        __stack_start = .;
        *(.stack)
        __stack_end = .;
    } > ram
}