~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 116 bytes
057ee98b — Rutherther chore: add generated bin, obj gitignore files 2 years ago 
                                                                                
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int add(int a, int b)
{
    return a + b;
}

void main()
{
    int a = 20;
    int b = 30;
    int c = add(a, b);
}