~ruther/verilog-riscv-semestral-project

ref: 02405eecab38bfa1d85e88d908b52a589ee53d30 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes
02405eec — Rutherther fix: force alu operation to addition for storing memory and pc 1 year, 7 months ago 
                                                                                
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module ram (
  input         clk, we,
  input [31:0]  a, wd,
  output [31:0] rd);

  reg [31:0]    RAM[0:127];

  assign rd = RAM[a[8:2]]; // word aligned

  always @(posedge clk)
    if(we) RAM[a[8:2]] <= wd;

endmodule
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