~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/testbench/tb_alu.sv -rw-r--r-- 1.0 KiB
79c7be5c — Rutherther 2 years ago main 
chore: remove unnecessary executable flags

Closes #4.
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c
2929a779 — Rutherther 2 years ago 
test: add basic testbenches