~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv 79c7be5c1c8ae2aea07f48d32abca650d24e8045

~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/testbench/tb_alu.sv -rw-r--r-- 1.0 KiB

79c7be5c — Rutherther 1 year, 3 months ago main

chore: remove unnecessary executable flags

Closes #4.

707b5bfc — Rutherther 1 year, 5 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 5 months ago

test: add basic testbenches