~ruther/verilog-riscv-semestral-project

ref: feat/misaligned-reads verilog-riscv-semestral-project/testbench/tb_cpu_program.sv -rwxr-xr-x 1.9 KiB 
tests: add register dump, printing

feat: add support for official tests

feat: add support for loading and saving ram from disk

feat: pass program to execute by parameter

feat: implement ebreak

Breaks the processor, can
exit the testcase

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

test: add cpu testbenches for c programs
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