~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 1.8 KiB
f8e4e3ed — Rutherther 2 years ago 
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
89310129 — Rutherther 2 years ago 
feat: implement pipeline
acf0f724 — Rutherther 2 years ago 
feat: implement sb, sh, lb, lh support via masking
b7fa590c — Rutherther 2 years ago 
chore: add cpu types for various sources

Better orientation by name instead of
number