~ruther/verilog-riscv-semestral-project: .gitignore f73ce77d4cbe9181f58b2e1c68b6525b9b67dd68

~ruther/verilog-riscv-semestral-project

ref: f73ce77d4cbe9181f58b2e1c68b6525b9b67dd68 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes

9c81ece2 — Rutherther 2 years ago

chore: add gitignore