~ruther/verilog-riscv-semestral-project: .gitignore 9c81ece23403b5cc0265b8012f82c935f3e64822

~ruther/verilog-riscv-semestral-project

ref: 9c81ece23403b5cc0265b8012f82c935f3e64822 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes

9c81ece2 — Rutherther 2 years ago

chore: add gitignore