~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv ee0204c8aee094b0d30256a61ba9400adb01dd5a

~ruther/verilog-riscv-semestral-project

ref: ee0204c8aee094b0d30256a61ba9400adb01dd5a verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 837 bytes

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 2 years ago

test: add basic testbenches