~ruther/verilog-riscv-semestral-project

ref: e44bfc9ea42a45f5776158e8e51c025f185b4f56 verilog-riscv-semestral-project/src/file_program_memory.sv -rwxr-xr-x 328 bytes
refactor: change program mem to file prog mem
feat: add program memory
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