~ruther/verilog-riscv-semestral-project: tests/official/env db85fb354b873f3ab5e5e936b4412a7d828f0ca7

~ruther/verilog-riscv-semestral-project

ref: db85fb354b873f3ab5e5e936b4412a7d828f0ca7 verilog-riscv-semestral-project/tests/official/env d---------

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests