~ruther/verilog-riscv-semestral-project (db85fb354b873f3ab5e5e936b4412a7d828f0ca7): tests/ - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

db85fb35 — Rutherther tests: fix ram and control_unit tests to match newest architecture 1 year, 5 months ago

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comp_list.lst

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custom/

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official/

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run.py

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test_types.py

928 bytes

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