~ruther/verilog-riscv-semestral-project: src/cpu_types.sv cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c

~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

b7fa590c — Rutherther 2 years ago

chore: add cpu types for various sources

Better orientation by name instead of
number