~ruther/verilog-riscv-semestral-project

ref: ca9604e2c8a9c44ccba5223ef095d84cd618bbe1 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.4 KiB
chore: add makefile for both verilog and c
feat: implement sb, sh, lb, lh support via masking
test: add simple cpu test
Do not follow this link