~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/testbench d---------
feat: implement ebreak

Breaks the processor, can
exit the testcase
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
test: add cpu testbenches for c programs
test: add ram test
chore: add makefile for both verilog and c
feat: implement sb, sh, lb, lh support via masking
test: add simple cpu test
test: add basic testbenches
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